Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to improve reliability. As FET (Field Effect Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Various detrimental device effects become more serious with successively decreasing device dimensions. For instance, with shortening gate lengths the so called short channel effects (SCEs), most notably drain-induced barrier lowering (DIBL) pose severe roadblocks to miniaturization. Also, parasitic capacitances, such as source and drain capacitance, stand in the way of device performance. At the same time, achieving ever higher gate capacitance runs into roadblocks, such as the depletion of the gate material, which traditionally has been poly-Si.
Traditionally, CMOS technologies advance from one generation to the next by scaling the gate length. This is accomplished by thinning the gate dielectric, increasing the channel doping and forming shallower source/drains. Thus far, gate dimensions have been scaled down to about 40 nm by using this approach for MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor) devices with poly-Si gate electrodes. Many elements needed to support the gate length scaling scheme are approaching physical limitations. For instance, making junctions highly conductive, and simultaneously of shallow depth, with the use of ion implantation and annealing becomes very difficult, due to dopant activation and diffusion effects. For standard processes, higher dopant activation (at higher temperatures) is usually accompanied by additional diffusion issues and concerns. Furthermore, excessive junction leakage may prevent channel doping from being increased beyond the concentration needed to control short channel effects for less than 40 nm gate length devices. Thus, a new device design, architecture, and processing methodology is needed to overcome the drawbacks associated with the prior art.